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19-2334; Rev 1; 4/02
2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCs
General Description
The MAX1136-MAX1139 low-power, 10-bit, multichannel analog-to-digital converters (ADCs) feature internal track/hold (T/H), voltage reference, clock, and an I2CTM-compatible 2-wire serial interface. These devices operate from a single supply of 2.7V to 3.6V (MAX1137/ MAX1139) or 4.5V to 5.5V (MAX1136/MAX1138) and require only 670A at the maximum sampling rate of 94.4ksps. Supply current falls below 230A for sampling rates under 46ksps. AutoShutdownTM powers down the devices between conversions, reducing supply current to less than 1A at low throughput rates. The MAX1136/MAX1137 have four analog input channels each, while the MAX1138/MAX1139 have 12 analog input channels each. The fully differential analog inputs are software configurable for unipolar or bipolar, and single ended or differential operation. The full-scale analog input range is determined by the internal reference or by an externally applied reference voltage ranging from 1V to V DD . The MAX1137/ MAX1139 feature a 2.048V internal reference and the MAX1136/MAX1138 feature a 4.096V internal reference. The MAX1136/MAX1137 are available in an 8-pin MAX package. The MAX1138/MAX1139 are available in a 16-pin QSOP package. The MAX1136-MAX1139 are guaranteed over the extended temperature range (-40C to +85C). For pin-compatible 12-bit parts, refer to the MAX1136-MAX1139 data sheet. For pin-compatible 8-bit parts, refer to the MAX1036-MAX1039 data sheet. 400kHz Fast Mode 1.7MHz High-Speed Mode o Single-Supply 2.7V to 3.6V (MAX1137/MAX1139) 4.5V to 5.5V (MAX1136/MAX1138) o Internal Reference 2.048V (MAX1137/MAX1139) 4.096V (MAX1136/MAX1138) o External Reference: 1V to VDD o Internal Clock o 4-Channel Single-Ended or 2-Channel Fully Differential (MAX1136/MAX1137) o 12-Channel Single-Ended or 6-Channel Fully Differential (MAX1138/MAX1139) o Internal FIFO with Channel-Scan Mode o Low Power 670A at 94.4ksps 230A at 40ksps 60A at 10ksps 6A at 1ksps 0.5A in Power-Down Mode o Software-Configurable Unipolar/Bipolar o Small Packages 8-Pin MAX (MAX1136/MAX1137) 16-Pin QSOP (MAX1138/MAX1139)
Features
o High-Speed I2C-Compatible Serial Interface
MAX1136-MAX1139
Applications
Hand-Held Portable Applications Medical Instruments Battery-Powered Test Equipment Solar-Powered Remote Systems Received-Signal-Strength Indicators System Supervision
Ordering Information
PART MAX1136EUA MAX1137EUA MAX1138EEE MAX1139EEE TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 8 MAX 8 MAX 16 QSOP 16 QSOP INL (LSB) 1 1 1 1
AutoShutdown is a trademark of Maxim Integrated Products, Inc. I2C is a trademark of Philips Corp.
Pin Configurations appear at end of data sheet. Typical Operating Circuit appears at end of data sheet. Selector Guide appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
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For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCs MAX1136-MAX1139
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V AIN0-AIN11, REF to GND ............-0.3V to the lower of (VDD + 0.3V) and 6V SDA, SCL to GND.....................................................-0.3V to +6V Maximum Current Into Any Pin .........................................50mA Continuous Power Dissipation (TA = +70C) 8-Pin MAX (derate 4.5mW/C above +70C) .............362mW 16-Pin QSOP (derate 8.3mW/C above +70C)........666.7mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 2.7V to 3.6V (MAX1137/MAX1139), VDD = 4.5V to 5.5V (MAX1136/MAX1138), VREF = 2.048V (MAX1137/MAX1139), VREF = 4.096V (MAX1136/MAX1138), CREF = 0.1F, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C. See Tables 1-5 for programming notation.)
PARAMETER DC ACCURACY (Note 1) Resolution Relative Accuracy Differential Nonlinearity Offset Error Offset-Error Temperature Coefficient Gain Error Gain-Temperature Coefficient Channel-to-Channel Offset Matching Channel-to-Channel Gain Matching DYNAMIC PERFORMANCE (fIN(SINE-WAVE) = 10kHz, VIN(P-P) = VREF, fSAMPLE = 94.4ksps) Signal-to-Noise Plus Distortion Total Harmonic Distortion Spurious Free Dynamic Range Full-Power Bandwidth Full-Linear Bandwidth CONVERSION RATE Conversion Time (Note 4) tCONV Internal clock External clock Internal clock, SCAN[1:0] = 01 Throughput Rate fSAMPLE Internal clock, SCAN[1:0] = 00 CS[3:0] = 1011 (MAX1138/MAX1139) External clock Track/Hold Acquisition Time 800 10.6 53 53 94.4 ns ksps 6.8 s SINAD THD SFDR SINAD > 57dB -3dB point Up to the 5th harmonic 60 -70 70 3.0 5.0 dB dB dB MHz MHz Relative to FSR (Note 3) Relative to FSR 0.3 0.1 0.1 0.3 1 INL DNL (Note 2) No missing codes over temperature 10 1 1 1 Bits LSB LSB LSB ppm/C LSB ppm/C LSB LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX1137/MAX1139), VDD = 4.5V to 5.5V (MAX1136/MAX1138), VREF = 2.048V (MAX1137/MAX1139), VREF = 4.096V (MAX1136/MAX1138), CREF = 0.1F, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C. See Tables 1-5 for programming notation.)
PARAMETER Internal Clock Frequency Aperture Delay (Note 5) ANALOG INPUT (AIN0-AIN11) Input-Voltage Range, SingleEnded and Differential (Note 6) Input Multiplexer Leakage Current Input Capacitance INTERNAL REFERENCE (Note 7) Reference Voltage Reference-Voltage Temperature Coefficient REF Short-Circuit Current REF Source Impedance EXTERNAL REFERENCE REF Input-Voltage Range REF Input Current Input High Voltage Input Low Voltage Input Hysteresis Input Current Input Capacitance Output Low Voltage POWER REQUIREMENTS Supply Voltage VDD MAX1137/MAX1139 MAX1136/MAX1138 fSAMPLE = 94.4ksps external clock fSAMPLE = 40ksps internal clock Supply Current IDD fSAMPLE = 10ksps internal clock fSAMPLE =1ksps internal clock Internal reference External reference Internal reference External reference Internal reference External reference Internal reference External reference 2.7 4.5 900 670 530 230 380 60 330 6 0.5 110 A 3.6 5.5 1150 900 V VREF IREF VIH VIL VHYST IIN CIN VOL ISINK = 3mA VIN 0 to VDD 15 0.4 0.1 VDD 10 (Note 8) fSAMPLE = 94.4ksps 0.7 VDD 0.3 VDD 1 VDD 40 V A V V V A pF V 1.5 VREF TCVREF TA = +25C MAX1137/MAX1139 MAX1136/MAX1138 1.968 3.939 2.048 4.096 25 2 2.128 4.256 V ppm/C mA k CIN Unipolar Bipolar ON/OFF leakage current, VAIN_ = 0 or VDD 0 0 0.01 22 VREF VREF/2 1 V A pF tAD External clock, fast mode External clock, high-speed mode SYMBOL CONDITIONS MIN TYP 2.8 60 30 MAX UNITS MHz ns
MAX1136-MAX1139
DIGITAL INPUTS/OUTPUTS (SCL, SDA)
Shutdown (internal reference OFF)
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCs MAX1136-MAX1139
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX1137/MAX1139), VDD = 4.5V to 5.5V (MAX1136/MAX1138), VREF = 2.048V (MAX1137/MAX1139), VREF = 4.096V (MAX1136/MAX1138), CREF = 0.1F, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C. See Tables 1-5 for programming notation.)
PARAMETER POWER REQUIREMENTS Power-Supply Rejection Ratio PSRR Full-scale input (Note 9) 0.01 0.5 LSB/V SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS (Figure 1)
(VDD = 2.7V to 3.6V (MAX1137/MAX1139), VDD = 4.5V to 5.5V (MAX1136/MAX1138), VREF = 2.048V (MAX1137/MAX1139), VREF = 4.096V (MAX1136/MAX1138), CREF = 0.1F, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C. See Tables 1-5 for programming notation.)
PARAMETER Serial Clock Frequency Bus Free Time Between a STOP (P) and a START (S) Condition Hold Time for START (S) Condition Low Period of the SCL Clock High Period of the SCL Clock Setup Time for a Repeated START Condition (Sr) Data Hold Time Data Setup Time Rise Time of Both SDA and SCL Signals, Receiving Fall Time of SDA Transmitting Setup Time for STOP (P) Condition Capacitive Load for Each Bus Line Pulse Width of Spike Suppressed Serial Clock Frequency Hold Time, Repeated START Condition (Sr) Low Period of the SCL Clock High Period of the SCL Clock Setup Time for a Repeated START Condition (Sr) Data Hold Time Data Setup Time SYMBOL fSCL tBUF tHD, STA tLOW tHIGH tSU, STA tHD, DAT tSU, DAT tR tF tSU, STO CB tSP fSCLH tHD, STA tLOW tHIGH tSU, STA tHD, DAT tSU, DAT (Note 10) (Note 12) 160 320 120 160 0 10 150 Measured from 0.3VDD to 0.7VDD Measured from 0.3VDD to 0.7VDD (Note 10) 1.3 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 0.6 400 50 1.7 300 300 900 CONDITIONS MIN TYP MAX 400 UNITS kHz s s s s s ns ns ns ns s pF ns MHz ns ns ns ns ns ns
TIMING CHARACTERISTICS FOR FAST MODE
TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (CB = 400pF, Note 11)
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCs
TIMING CHARACTERISTICS (Figure 1) (continued)
(VDD = 2.7V to 3.6V (MAX1137/MAX1139), VDD = 4.5V to 5.5V (MAX1136/MAX1138), VREF = 2.048V (MAX1137/MAX1139), VREF = 4.096V (MAX1136/MAX1138), CREF = 0.1F, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C. See Tables 1-5 for programming notation.)
PARAMETER Rise Time of SCL Signal (Current Source Enabled) Rise Time of SCL Signal after Acknowledge Bit Fall Time of SCL Signal Rise Time of SDA Signal Fall Time of SDA Signal Setup Time for STOP (P) Condition Capacitive Load for Each Bus Line Pulse Width of Spike Suppressed SYMBOL tRCL tRCL1 tFCL tRDA tFDA tSU, STO CB tSP (Notes 10 and 12) 0 CONDITIONS Measured from 0.3VDD to 0.7VDD Measured from 0.3VDD to 0.7VDD Measured from 0.3VDD to 0.7VDD Measured from 0.3VDD to 0.7VDD Measured from 0.3VDD to 0.7VDD MIN 20 20 20 20 20 160 400 10 TYP MAX 80 160 80 160 160 UNITS ns ns ns ns ns ns pF ns
MAX1136-MAX1139
Note 1: For DC accuracy, the MAX1136/MAX1138 are tested at VDD = 5V and the MAX1137/MAX1139 are tested at VDD = 3V. All devices are configured for unipolar, single-ended inputs. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offsets have been calibrated. Note 3: Offset nulled. Note 4: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion time does not include acquisition time. SCL is the conversion clock in the external clock mode. Note 5: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant. Note 6: The absolute input-voltage range for the analog inputs (AIN0-AIN11) is from GND to VDD. Note 7: When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11) decouple AIN_/REF to GND with a 0.01F capacitor. Note 8: ADC performance is limited by the converter's noise floor, typically 300VP-P. Note 9: Measured as for the MAX1137/MAX1139
2N - 1 [VFS (3.6V) - VFS (2.7V)] x VREF (3.6V - 2.7V)
and for the MAX1136/MAX1138
2N - 1 [VFS (5.5V) - VFS (4.5V)] x VREF (5.5V - 4.5V)
Note 10: A master device must provide a data hold time for SDA (referred to VIL of SCL) in order to bridge the undefined region of SCL's falling edge (see Figure 1). Note 11: CB = total capacitance of one bus line in pF. Note 12: fSCL must meet the minimum clock low time plus the rise/fall times.
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCs MAX1136-MAX1139
Typical Operating Characteristics
(VDD = 3.3V (MAX1137/MAX1139), VDD = 5V (MAX1136/MAX1138), fSCL = 1.7MHz, external clock, fSAMPLE = 94.4ksps, singleended, unipolar, TA = +25C, unless otherwise noted.)
DIFFERENTIAL NONLINEARITY vs. DIGITAL CODE
MAX1136 toc01
INTEGRAL NONLINEARITY vs. DIGITAL CODE
MAX1136 toc02
FFT PLOT
-20 -40 AMPLITUDE (dBc) -60 -80 -100 -120 -140 -160 0 10k 20k 30k 40k 50k fSAMPLE = 94.4ksps fIN = 10kHz
MAX1136 toc03
0.3 0.2 0.1 DNL (LSB)
0.5 0.4 0.3 0.2 INL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4
0
0 -0.1 -0.2 -0.3 0 200 400 600 800 1000 DIGITAL OUTPUT CODE
-0.5 0 200 400 600 800 1000 DIGITAL OUTPUT CODE
FREQUENCY (Hz)
SUPPLY CURRENT vs. TEMPERATURE (MAX1138/MAX1139)
MAX1136 toc04
SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1136 toc05
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
0.45 0.40 SUPPLY CURRENT (A) 0.35 0.30 0.25 0.20 0.15 0.10 0.05 MAX1139 MAX1138
MAX1136 toc06
800 750 700 SUPPLY CURRENT (A) 650 600 550 500 450 400 350 300 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (C) EXTERNAL REFERENCE MAX1139/1137 INTERNAL REFERENCE EXTERNAL REFERENCE INTERNAL REFERENCE MAX1138/1136 SETUP BYTE EXT REF: 10111011 INT REF: 11011011 MAX1139/1137 MAX1138/1136
0.6 SDA = SCL = VDD 0.5 0.4 IDD (A) 0.3 0.2 0.1 0 2.7 3.2 3.7 4.2 4.7 5.2 INPUT VOLTAGE (V)
0.50
0 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (C)
AVERAGE SUPPLY CURRENT vs. CONVERSION RATE (EXTERNAL CLOCK)
800 750 700 650 600 550 500 450 400 350 300 250 200 0
MAX1136 toc07
INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
MAX1136 toc08
NORMALIZED REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
1.00008 1.00006 VREF NORMALIZED 1.00004 1.00002 1.00000 0.99998 0.99996 MAX1139/MAX1137, NORMALIZED TO REFERENCE VALUE AT VDD = 3.3V 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 VDD (V) MAX1138/MAX1136, NORMALIZED TO REFERENCE VALUE AT VDD = 5V
MAX1136 toc09
1.0010 1.0008 1.0006
VREF NORMALIZED
A) INTERNAL REFERENCE ALWAYS ON B) EXTERNAL REFERENCE
A
NORMALIZED TO REFERENCE VALUE AT +25C MAX1138
1.00010
AVERAGE IDD (A)
1.0004 1.0002 1.0000 0.9998 0.9996 0.9994 MAX1139
B
0.99994 0.99992 0.99990
MAX1138 10 20 30 40 50 60 70 80 90 100 CONVERSION RATE (ksps)
0.9992 0.9990 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (C)
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCs MAX1136-MAX1139
Typical Operating Characteristics (continued)
(VDD = 3.3V (MAX1137/MAX1139), VDD = 5V (MAX1136/MAX1138), fSCL = 1.7MHz, external clock, fSAMPLE = 94.4ksps, singleended, unipolar, TA = +25C, unless otherwise noted.)
OFFSET ERROR vs. TEMPERATURE
MAX1136 toc10
OFFSET ERROR vs. SUPPLY VOLTAGE
-0.1 -0.2 OFFSET ERROR (LSB) -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0
MAX1136 toc11
0 -0.1 -0.2 OFFSET ERROR (LSB) -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (C)
0
2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 VDD (V)
GAIN ERROR vs. TEMPERATURE
MAX1136 toc12
GAIN ERROR vs. SUPPLY VOLTAGE
0.9 0.8 GAIN ERROR (LSB) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
MAX1136 toc13
1.0 0.9 0.8 GAIN ERROR (LSB) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (C)
1.0
2.7
3.2
3.7
4.2 VDD (V)
4.7
5.2
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCs MAX1136-MAX1139
Pin Description
PIN MAX1136 MAX1137 1, 2, 3 -- -- 4 -- 5 6 7 8 MAX1138 MAX1139 1, 2, 3 4-8 16, 15, 14 -- 13 9 10 11 12 NAME AIN0-AIN2 AIN3-AIN7 AIN8-AIN10 AIN3/REF AIN11/REF SCL SDA GND VDD Analog Input 3/Reference Input or Output. Selected in the Setup Register. (See Tables 1 and 6.) Analog Input 11/Reference Input or Output. Selected in the Setup Register. (See Tables 1 and 6.) Clock Input Data Input/Output Ground Positive Supply. Bypass to GND with a 0.1F capacitor. Analog Inputs DESCRIPTION
A. F/S-MODE 2-WIRE SERIAL INTERFACE TIMING tR tF t
SDA
tSU.DAT tLOW
tHD.DAT tSU.STA
tHD.STA tSU.STO
tBUF
SCL
tHD.STA tR S
tHIGH tF Sr A P S
B. HS-MODE 2-WIRE SERIAL INTERFACE TIMING tRDA tFDA
SDA
tSU.DAT tLOW
tHD.DAT tSU.STA
tHD.STA
tBUF tSU.STO
SCL
tHD.STA tRCL S
tHIGH tFCL Sr A tRCL1 P S
HS-MODE
F/S-MODE
Figure 1. 2-Wire Serial Interface Timing 8 _______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCs MAX1136-MAX1139
SDA SCL INPUT SHIFT REGISTER VDD SETUP REGISTER GND CONFIGURATION REGISTER CONTROL LOGIC INTERNAL OSCILLATOR
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11/REF
T/H
10-BIT ADC
OUTPUT SHIFT REGISTER AND RAM
ANALOG INPUT MUX
REF
REFERENCE 4.096V (MAX1138) 2.048V (MAX1139)
MAX1138 MAX1139
Figure 2. MAX1138/MAX1139 Functional Diagram
VDD IOL
1.7MHz. Figure 2 shows the simplified internal structure for the MAX1138/MAX1139.
Power Supply
The MAX1136-MAX1139 operates from a single supply and consumes 670A (typ) at sampling rates up to 94.4ksps. The MAX1137/MAX1139 feature a 2.048V internal reference and the MAX1136/MAX1138 feature a 4.096V internal reference. All devices can be configured for use with an external reference from 1V to VDD.
SDA
VOUT 400pF IOH
Analog Input and Track/Hold
The MAX1136-MAX1139 analog-input architecture contains an analog-input multiplexer (mux), a fully differential track-and-hold (T/H) capacitor, T/H switches, a comparator, and a fully differential switched capacitive digital-to-analog converter (DAC) (Figure 4). In single-ended mode the analog-input multiplexer connects C T/H between the analog input selected by CS[3:0] (see the Configuration Setup Bytes section) and GND (Table 3). In differential mode, the analoginput multiplexer connects CT/H to the "+" and "-" analog inputs selected by CS[3:0] (Table 4). During the acquisition interval the T/H switches are in the track position and CT/H charges to the analog input
9
Figure 3. Load Circuit
Detailed Description
The MAX1136-MAX1139 analog-to-digital converters (ADCs) use successive-approximation conversion techniques and fully differential input track/hold (T/H) circuitry to capture and convert an analog signal to a serial 12-bit digital output. The MAX1136/MAX1137 are 4-channel ADCs, and the MAX1138/MAX1139 are 12-channel ADCs. These devices feature a high-speed 2-wire serial interface supporting data rates up to
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCs
signal. At the end of the acquisition interval, the T/H switches move to the hold position retaining the charge on CT/H as a stable sample of the input signal. During the conversion interval, the switched capacitive DAC adjusts to restore the comparator input voltage to 0V within the limits of 10-bit resolution. This action requires 10 conversion clock cycles and is equivalent to transferring a charge of 11pF (VIN+ - VIN-) from CT/H to the binary weighted capacitive DAC, forming a digital representation of the analog input signal. Sufficiently low source impedance is required to ensure an accurate sample. A source impedance of up to 1.5k does not significantly degrade sampling accuracy. To minimize sampling errors with higher source impedances, connect a 100pF capacitor from the analog input to GND. This input capacitor forms an RC filter with the source impedance limiting the analog-input bandwidth. For larger source impedances, use a buffer amplifier to maintain analog-input signal integrity and bandwidth. When operating in internal clock mode, the T/H circuitry enters its tracking mode on the eighth rising clock edge of the address byte (see the Slave Address section). The T/H circuitry enters hold mode on the falling clock edge of the acknowledge bit of the address byte (the ninth clock pulse). A conversion, or series of conversions, are then internally clocked and the MAX1136-MAX1139 holds SCL low. With external clock mode, the T/H circuitry enters track mode after a valid address on the rising edge of the clock during the read (R/W = 1) bit. Hold mode is then entered on the rising edge of the second
MAX1136-MAX1139
clock pulse during the shifting out of the first byte of the result. The conversion is performed during the next 10 clock cycles. The time required for the T/H circuitry to acquire an input signal is a function of the input sample capacitance. If the analog-input source impedance is high, the acquisition time constant lengthens and more time must be allowed between conversions. The acquisition time (tACQ) is the minimum time needed for the signal to be acquired. It is calculated by: tACQ 9 (RSOURCE + RIN) CIN where RSOURCE is the analog-input source impedance, RIN = 2.5k, and CIN = 22pF. tACQ is 1.5/fSCL for internal clock mode and tACQ = 2/fSCL for external clock mode.
Analog Input Bandwidth
The MAX1136-MAX1139 feature input-tracking circuitry with a 5MHz small-signal bandwidth. The 5MHz input bandwidth makes it possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC's sampling rate by using under sampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended.
Analog Input Range and Protection
Internal protection diodes clamp the analog input to VDD and GND. These diodes allow the analog inputs to
ANALOG INPUT MUX AIN0
HOLD
REF CT/H
TRACK
AIN1
TRACK
AIN2
HOLD
TRACK
HOLD
CAPACITIVE DAC
VDD/2
AIN3/REF
TRACK
HOLD
TRACK
GND CT/H REF
CAPACITIVE DAC
HOLD
MAX1136 MAX1137
Figure 4. Equivalent Input Circuit 10 ______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCs
swing from (GND - 0.3V) to (VDD + 0.3V) without causing damage to the device. For accurate conversions the inputs must not go more than 50mV below GND or above VDD. START and STOP Conditions section). Both SDA and SCL remain high when the bus is not busy. START and STOP Conditions The master initiates a transmission with a START condition (S), a high-to-low transition on SDA while SCL is high. The master terminates a transmission with a STOP condition (P), a low-to-high transition on SDA while SCL is high (Figure 5). A repeated START condition (Sr) can be used in place of a STOP condition to leave the bus active and the mode unchanged (see HS-mode).
S Sr P
MAX1136-MAX1139
Single-Ended/Differential Input
The SGL/DIF of the configuration byte configures the MAX1136-MAX1139 analog-input circuitry for singleended or differential inputs (Table 2). In single-ended mode (SGL/DIF = 1), the digital conversion results are the difference between the analog input selected by CS[3:0] and GND (Table 3). In differential mode (SGL/ DIF = 0) the digital conversion results are the difference between the "+" and the "-" analog inputs selected by CS[3:0] (Table 4).
Unipolar/Bipolar
When operating in differential mode, the BIP/UNI bit of the setup byte (Table 1) selects unipolar or bipolar operation. Unipolar mode sets the differential input range from 0 to VREF. A negative differential analog input in unipolar mode will cause the digital output code to be zero. Selecting bipolar mode sets the differential input range to VREF/2. The digital output code is binary in unipolar mode and two's complement in bipolar mode, see the Transfer Functions section. In single-ended mode the MAX1136-MAX1139 will always operate in unipolar mode irrespective of BIP/UNI. The analog inputs are internally referenced to GND with a full-scale input range from 0 to VREF.
SDA
SCL
Figure 5. START and STOP Conditions
2-Wire Digital Interface
The MAX1136-MAX1139 feature a 2-wire interface consisting of a serial data line (SDA) and serial clock line (SCL). SDA and SCL facilitate bidirectional communication between the MAX1136-MAX1139 and the master at rates up to 1.7MHz. The MAX1136-MAX1139 are slaves that transfer and receive data. The master (typically a microcontroller) initiates data transfer on the bus and generates the SCL signal to permit that transfer. SDA and SCL must be pulled high. This is typically done with pullup resistors (750 or greater) (see the Typical Operating Circuit). Series resistors (RS) are optional. They protect the input architecture of the MAX1136- MAX1139 from high voltage spikes on the bus lines, minimize crosstalk, and undershoot of the bus signals. Bit Transfer One data bit is transferred during each SCL clock cycle. A minimum of eighteen clock cycles are required to transfer the data in or out of the MAX1136-MAX1139. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is stable are considered control signals (see the
Acknowledge Bits Data transfers are acknowledged with an acknowledge bit (A) or a not-acknowledge bit (A). Both the master and the MAX1136-MAX1139 (slave) generate acknowledge bits. To generate an acknowledge, the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse (Figure 6). To generate a not-acknowledge, the receiver allows SDA to be pulled high before the rising edge of the acknowledge-related clock pulse and leaves SDA high during the high period of the clock pulse. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer the bus master should reattempt communication at a later time.
S
NOT ACKNOWLEDGE
SDA ACKNOWLEDGE SCL 1 2 8 9
Figure 6. Acknowledge Bits
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11
2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCs MAX1136-MAX1139
DEVICE MAX1136/MAX1137 MAX1138/MAX1139 SLAVE ADDRESS 0110100 0110101
MAX1136/MAX1137 S 0 1 1
SLAVE ADDRESS 0 1 0 0 R/W A
SDA
SCL
1
2
3
4
5
6
7
8
9
Figure 7. MAX1136/MAX1137 Slave Address Byte
Slave Address A bus master initiates communication with a slave device by issuing a START condition followed by a slave address. When idle, the MAX1136-MAX1139 continuously wait for a START condition followed by their slave address. When the MAX1136-MAX1139 recognize their slave address, they are ready to accept or send data. The slave address has been factory programmed and is always 0110100 for the MAX1136/MAX1137, and 0110101 for MAX1138/MAX1139 (Figure 7). The least significant bit (LSB) of the address byte (R/W) determines whether the master is writing to or reading from the MAX1136-MAX1139 (R/W = 0 selects a write condition, R/W = 1 selects a read condition). After receiving the address, the MAX1136-MAX1139 (slave) issues an acknowledge by pulling SDA low for one clock cycle. Bus Timing At power-up, the MAX1136-MAX1139 bus timing is set for fast mode (F/S-mode) which allows conversion rates
HS-MODE MASTER CODE S 0 0 0 0 1 X
up to 22.2ksps. The MAX1136-MAX1139 must operate in high-speed mode (HS-mode) to achieve conversion rates up to 94.4ksps. Figure 1 shows the bus timing for the MAX1136-MAX1139's 2-wire interface. HS-Mode At power-up, the MAX1136-MAX1139 bus timing is set for F/S-mode. The bus master selects HS-mode by addressing all devices on the bus with the HS-mode master code 0000 1XXX (X = don't care). After successfully receiving the HS-mode master code, the MAX1136-MAX1139 issue a not-acknowledge allowing SDA to be pulled high for one clock cycle (Figure 8). After the not-acknowledge, the MAX1136-MAX1139 are in HS-mode. The bus master must then send a repeated START followed by a slave address to initiate HS-mode communication. If the master generates a STOP condition the MAX1136-MAX1139 returns to F/S-mode.
X
X
A
Sr
SDA
SCL
F/S-MODE
HS-MODE
Figure 8. F/S-Mode to HS-Mode Transfer 12 ______________________________________________________________________________________
2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCs
Configuration/Setup Bytes (Write Cycle) A write cycle begins with the bus master issuing a START condition followed by seven address bits (Figure 7) and a write bit (R/W = 0). If the address byte is successfully received, the MAX1136-MAX1139 (slave) issues an acknowledge. The master then writes to the slave. The slave recognizes the received byte as the setup byte (Table 1) if the most significant bit (MSB) is 1. If the MSB is 0, the slave recognizes that byte as the configuration byte (Table 3). The master can write either one or two bytes to the slave in any order (setup byte then configuration byte; configuration byte then setup byte; setup byte or configuration byte only; Figure 9). If the slave receives a byte successfully, it issues an acknowledge. The master ends the write cycle by issuing a STOP condition or a repeated START condition. When operating in HS-mode, a STOP condition returns the bus into F/S-mode (see the HS-Mode section).
MAX1136-MAX1139
MASTER TO SLAVE SLAVE TO MASTER A. ONE- BYTE WRITE CYCLE 1 S 7 SLAVE ADDRESS 11 8 1 1 NUMBER OF BITS
SETUP OR WA A P or Sr CONFIGURATION BYTE
MSB DETERMINES WHETHER SETUP OR CONFIGURATION BYTE B. TWO-BYTE WRITE CYCLE 1 S 7 SLAVE ADDRESS 11 WA 8 SETUP OR CONFIGURATION BYTE 1 A 8 1 1 NUMBER OF BITS
SETUP OR A P or Sr CONFIGURATION BYTE
MSB DETERMINES WHETHER SETUP OR CONFIGURATION BYTE
Figure 9. Write Cycle
Table 1. Setup Byte Format
BIT 7 (MSB) REG BIT 7 6 5 4 3 2 1 0 BIT 6 SEL2 NAME REG SEL2 SEL1 SEL0 CLK BIP/UNI RST X 1 = external clock, 0 = internal clock. Defaulted to 0 at power-up. 1 = bipolar, 0 = unipolar. Defaulted to 0 at power-up. 1 = no action, 0 = resets the configuration register to default. Setup register remains unchanged. Don't care, can be set to 1 or 0. Three bits select the reference voltage and the state of AIN_/REF (Table 6). Defaulted to 000 at power-up. BIT 5 SEL1 BIT 4 SEL0 BIT 3 CLK BIT 2 BIP/UNI BIT 1 RST BIT 0 (LSB) X
DESCRIPTION Register bit. 1 = setup byte, 0 = configuration byte (see Table 2).
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13
2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCs MAX1136-MAX1139
Table 2. Configuration Byte Format
BIT 7 (MSB) REG BIT 7 6 5 4 3 2 1 0 BIT 6 SCAN1 NAME REG SCAN1 SCAN0 CS3 CS2 CS1 CS0 SGL/DIF 1 = single-ended, 0 = differential (Tables 3 and 4). Defaulted to 1 at power-up. See the SingleEnded/Differential Input section. Channel select bits. Four bits select which analog input channels are to be used for conversion (Tables 3 and 4). Defaulted to 0000 at power-up. For MAX1136/MAX1137, CS3 and CS2 are internally set to 0. BIT 5 SCAN0 BIT 4 CS3 BIT 3 CS2 BIT 2 CS1 BIT 1 CS0 BIT 0 (LSB) SGL/DIF
DESCRIPTION Register bit 1= setup byte (see Table 1), 0 = configuration byte Scan select bits. Two bits select the scanning configuration (Table 5). Defaulted to 00 at power-up.
Table 3. Channel Selection in Single-Ended Mode (SGL/DIF = 1)
CS31 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CS21 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RESERVED RESERVED RESERVED RESERVED AIN0 + + + + + + + + + + + + AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN112 GND -
1. For MAX1136/MAX1137, CS3 and CS2 are internally set to 0. 2. When SEL1 = 1, a single-ended read of AIN3/REF (MAX1136/MAX1137) or AIN11/REF (MAX1138/MAX1139) will be ignored; scan will stop at AIN2 or AIN10.
14
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCs MAX1136-MAX1139
Table 4. Channel Selection in Differential Mode (SGL/DIF = 0)
CS31 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CS21 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RESERVED RESERVED RESERVED RESERVED AIN0 + AIN1 + + + + + + + + + + + AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN112
1. For MAX1136/MAX1137, CS3 and CS2 are internally set to 0. 2. When SEL1 = 1, a differential read between AIN2 and AIN3/REF (MAX1136/MAX1137) or AIN10 and AIN11/REF (MAX1138/MAX1139) will return the difference between GND and AIN2 or AIN10, respectively. For example, a differential read of 1011 will return the negative difference between AIN10 and GND. In differential scanning, the address increments by 2 until limit set by CS3:CS1 has been reached.
Data Byte (Read Cycle) A read cycle must be initiated to obtain conversion results. Read cycles begin with the bus master issuing a START condition followed by seven address bits and a read bit (R/W = 1). If the address byte is successfully received, the MAX1136-MAX1139 (slave) issues an acknowledge. The master then reads from the slave. The result is transmitted in two bytes; first six bits of the first byte are high, then MSB through LSB are consecutively clocked out. After the master has received the byte(s) it can issue an acknowledge if it wants to continue reading or a not-acknowledge if it no longer wishes to read. If the MAX1136-MAX1139 receive a notacknowledge, they release SDA allowing the master to generate a STOP or a repeated START condition. See the Clock Mode and Scan Mode sections for detailed information on how data is obtained and converted. Clock Modes The clock mode determines the conversion clock and the data acquisition and conversion time. The clock mode also affects the scan mode. The state of the setup byte's CLK bit determines the clock mode (Table 1).
At power-up the MAX1136-MAX1139 are defaulted to internal clock mode (CLK = 0). Internal Clock When configured for internal clock mode (CLK = 0), the MAX1136-MAX1139 use their internal oscillator as the conversion clock. In internal clock mode, the MAX1136- MAX1139 begin tracking the analog input after a valid address on the eighth rising edge of the clock. On the falling edge of the ninth clock the analog signal is acquired and the conversion begins. While converting the analog input signal, the MAX1136-MAX1139 holds SCL low (clock stretching). After the conversion completes, the results are stored in internal memory. If the scan mode is set for multiple conversions, they will all happen in succession with each additional result stored in memory.The MAX1136/MAX1137 contain four 10-bit blocks of memory, and the MAX1138/MAX1139 contain twelve 10-bit blocks of memory. Once all conversions are complete, the MAX1136-MAX1139 release SCL allowing it to be pulled high. The master may now clock the results out of the memory in the same order the scan conversion has been done at a clock rate of up to 1.7MHz. SCL will be stretched for a maximum of 7.6s per channel (see Figure 10).
15
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCs MAX1136-MAX1139
MASTER TO SLAVE SLAVE TO MASTER
A. SINGLE CONVERSION WITH INTERNAL CLOCK 1 S 7 SLAVE ADDRESS tACQ tCONV 11 RA CLOCK STRETCH 8 RESULT 2 MSBs A 8 RESULT 8 LSBs 1 1 NUMBER OF BITS
A P or Sr
B. SCAN MODE CONVERSIONS WITH INTERNAL CLOCK 1 S 7 SLAVE ADDRESS tACQ1 tCONV1 11 RA CLOCK STRETCH CLOCK STRETCH 8 1 8 1 8 1 8 1 1 NUMBER OF BITS
RESULT 1 ( 2MSBs) A RESULT 1 (8 LSBs) A
RESULT N (8MSBs) A RESULT N (8LSBs) A P or Sr
tACQ2 tCONV2
tACQN tCONVN
Figure 10. Internal Clock Mode Read Cycles
The device memory contains all of the conversion results when the MAX1136-MAX1139 release SCL. The converted results are read back in a first-in-first-out (FIFO) sequence. If AIN_/REF is set to be a reference input or output (SEL1 = 1, Table 6), AIN_/REF will be excluded from a multichannel scan. The memory contents can be read continuously. If reading continues past the result stored in memory, the pointer will wrap around and point to the first result. Note that only the
current conversion results will be read from memory. The device must be addressed with a read command to obtain new conversion results. The internal clock mode's clock stretching quiets the SCL bus signal reducing the system noise during conversion. Using the internal clock also frees the bus master (typically a microcontroller) from the burden of running the conversion clock, allowing it to perform other tasks that do not need to use the bus.
MASTER TO SLAVE SLAVE TO MASTER
A. SINGLE CONVERSION WITH EXTERNAL CLOCK 1 S 7 SLAVE ADDRESS 11 RA 8 RESULT (2 MSBs) tACQ tCONV 1 A 8 RESULT (8 LSBs) 1 A 1 P OR Sr NUMBER OF BITS
B. SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK 1 S 7 SLAVE ADDRESS 11 RA 8 RESULT 1 (2 MSBs) tACQ1 tCONV1 1 A 8 RESULT 2 (8 LSBs) 1 A tACQ2 8 RESULT N (2 MSBs) tACQN tCONVN 1 A 8 RESULT N (8 LSBs) 1 1 NUMBER OF BITS
A P OR Sr
Figure 11. External Clock Mode Read Cycle
16
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCs MAX1136-MAX1139
Table 5. Scanning Configuration
SCAN1 0 0 SCAN0 0 1 SCANNING CONFIGURATION Scans up from AIN0 to the input selected by CS3-CS0. When CS3-CS0 exceeds 11, the scanning will stop at AIN11. When AIN_/REF is set to be a REF in/out, scanning will stop at AIN3 and AIN10. *Converts the input selected by CS3-CS0 eight times. (See Tables 3 and 4) Scans up from AIN2 to the input selected by CS1 and CS0. When CS1 and CS0 are set for AIN0-AIN2 the scanning will stop at AIN2 (MAX1136/MAX1137). When AIN_/REF is set to be a REF in/out, scanning will stop at AIN3 and AIN10. Scans up from AIN6 to the input selected by CS3-CS0. When CS3-CS0 is set for AIN0-AIN6 scanning will stop at AIN6 (MAX1138/MAX1139). When AIN_/REF is set to be a REF in/out, scanning will stop at AIN3 and AIN10. *Converts channel selected by CS3-CS0.
1
0
1
1
*When operating in external clock mode there is no difference between SCAN[1:0] = 01 and SCAN[1:0] = 11 and converting will occur perpetually until not acknowledge occurs.
External Clock When configured for external clock mode (CLK = 1), the MAX1136-MAX1139 use the SCL as the conversion clock. In external clock mode, the MAX1136-MAX1139 begin tracking the analog input on the ninth rising clock edge of a valid slave address byte. Two SCL clock cycles later the analog signal is acquired and the conversion begins. Unlike internal clock mode, converted data is available immediately after the first four empty high bits. The device will continuously convert input channels dictated by the scan mode until given a not acknowledge. There is no need to re-address the device with a read command to obtain new conversion results (see Figure 11). The conversion must complete in 1ms or droop on the track-and-hold capacitor will degrade conversion results. Use internal clock mode if the SCL clock period exceeds 60s. The MAX1136-MAX1139 must operate in external clock mode for conversion rates from 40ksps to 94.4ksps. Below 40ksps internal clock mode is recommended due to much smaller power consumption. Scan Mode SCAN0 and SCAN1 of the configuration byte set the scan mode configuration. Table 5 shows the scanning configurations. If AIN_/REF is set to be a reference input or output (SEL1 = 1, Table 6), AIN_/REF will be excluded from a multichannel scan. The scanned results are written to memory in the same order as the conversion. Read the results from memory in the order they were converted. Each result needs a 2-byte transmission, the first byte begins with six empty bits during which SDA is left high. Each byte has to be acknowledged by the master or the memory transmission will
be terminated. It is not possible to read the memory independently of conversion.
Applications Information
Power-On Reset
The configuration and setup registers (Tables 1 and 2) will default to a single-ended, unipolar, single-channel conversion on AIN0 using the internal clock with VDD as the reference and AIN_/REF configured as an analog input. The memory contents are unknown after power-up. Automatic Shutdown SEL[2:0] of the setup byte (Table 1 and Table 6) control the state of the reference and AIN_/REF. If automatic shutdown is selected (SEL[2:0] = 100), shutdown will occur between conversions when the MAX1136- MAX1139 are idle. When operating in external clock mode, a STOP, not-acknowledge or repeated START, condition must be issued to place the devices in idle mode and benefit from automatic shutdown. A STOP condition is not necessary in internal clock mode to benefit from automatic shutdown because power-down occurs once all contents are written to memory (Figure 10). All analog circuitry is inactive in shutdown and supply current is less than 0.5A (typ). The digital conversion results are maintained in memory during shutdown and are available for access through the serial interface at any time prior to a STOP or a repeated START condition. When idle the MAX1136-MAX1139 continuously wait for a START condition followed by their slave address (see Slave Address section). Upon reading a valid address byte the MAX1136-MAX1139 power-up. The internal reference requires 10ms to wake up, so when using the internal reference it should be powered up
17
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCs MAX1136-MAX1139
Table 6. Reference Voltage and AIN_/REF Format
SEL2 0 0 1 1 1 1 SEL1 0 1 0 0 1 1 SEL0 X X 0 1 0 1 REFERENCE VOLTAGE VDD External Reference Internal Reference Internal Reference Internal Reference Internal Reference AIN_/REF Analog Input Reference Input Analog Input Analog Input Reference Output Reference Output INTERNAL REFERENCE STATE Always Off Always Off Always Off Always On Always Off Always On
10ms prior to conversion or powered continuously. Wake-up is invisible when using an external reference or VDD as the reference. Automatic shutdown results in dramatic power savings, particularly at slow conversion rates and with internal clock. For example, at a conversion rate of 10ksps, the average supply current for the MAX1137 is 60A (typ) and drops to 6A (typ) at 1ksps. At 0.1ksps the average supply current is just 1A, or a minuscule 3W of power consumption, see Average Supply Current vs. Conversion Rate in the Typical Operating Characteristics).
Transfer Functions
Output data coding for the MAX1136-MAX1139 is binary in unipolar mode and two's complement in bipolar mode with 1LSB = (VREF/2N) where `N' is the number of bits (10). Code transitions occur halfway between successive-integer LSB values. Figure 12 and Figure 13 show the input/output (I/O) transfer functions for unipolar and bipolar operations, respectively.
Layout, Grounding, and Bypassing
Only use PC boards. Wire-wrap configurations are not recommended since the layout should ensure proper separation of analog and digital traces. Do not run analog and digital lines parallel to each other, and do not layout digital signal paths underneath the ADC package. Use separate analog and digital PC board ground sections with only one star point (Figure 14) connecting the two ground systems (analog and digital). For lowest noise operation, ensure the ground return to the star
Reference Voltage
SEL[2:0] of the setup byte (Table 1) control the reference and the AIN_/REF configuration (Table 6). When AIN_/REF is configured to be a reference input or reference output (SEL1 = 1), differential conversions on AIN_/REF appear as if AIN_/REF is connected to GND (see Note 2 and Table 4). Single-ended conversion in scan mode on AIN_/REF will be ignored by internal limiter, which sets the highest available channel at AIN2 or AIN10. Internal Reference The internal reference is 4.096V for the MAX1136/ MAX1138 and 2.048V for the MAX1137/MAX1139. SEL1 of the setup byte controls whether AIN_/REF is used for an analog input or a reference (Table 6). When AIN_/REF is configured to be an internal reference output (SEL[2:1] = 11), decouple AIN_/REF to GND with a 0.1F capacitor. Once powered up, the reference always remains on until reconfigured. The reference should not be used to supply current for external circuitry. External Reference The external reference can range from 1V to VDD. For maximum conversion accuracy, the reference must be able to deliver up to 40A and have an output impedance of 500 or less. If the reference has a higher output impedance or is noisy, bypass it to GND as close to AIN_/REF as possible with a 0.1F capacitor.
18
OUTPUT CODE 111...111 111...110 FS = REF + GND ZS = GND
FULL-SCALE TRANSITION
100...010 100...001 100...000 011...111 011...110 011...101 1LSB = VREF 1024
000...001 000...000 0 (GND) 1 512 INPUT VOLTAGE (LSB) 1 FS - 2 LSB
Figure 12. Unipolar Transfer Function
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCs MAX1136-MAX1139
OUTPUT CODE 011...111 011...110 V FS = REF + AIN2 ZS = AIN-FS = -VREF + AIN2 VREF 1LSB = 1024 3V OR 5V VLOGIC = 3V/5V GND SUPPLIES
000...010 000...001 000...000 111...111 111...110 111...101
R* = 5
4.7F
0.1F VDD GND 3V/5V DGND
100...001 100...000 -FS + 1 LSB 2 V AIN- REF 2 AININPUT VOLTAGE (LSB) +FS - 1LSB *OPTIONAL
MAX1136- MAX1139
DIGITAL CIRCUITRY
Figure 13. Bipolar Transfer Function
Figure 14. Power-Supply Grounding Connection
ground's power supply is low impedance and as short as possible. Route digital signals far away from sensitive analog and reference inputs. High-frequency noise in the power supply (VDD) could influence the proper operation of the ADC's fast comparator. Bypass VDD to the star ground with a network of two parallel capacitors, 0.1F and 4.7F, located as close as possible to the MAX1136-MAX1139 power-supply pin. Minimize capacitor lead length for best supply noise rejection, and add an attenuation resistor (5) in series with the power supply, if it is extremely noisy.
Aperture Delay
Aperture delay (tAD) is the time between the falling edge of the sampling clock and the instant when an actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the fullscale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N Bits): SNRMAX[dB] = 6.02dB N + 1.76dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The MAX1136- MAX1139's INL is measured using the endpoint.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency's RMS amplitude to RMS equivalent of all other ADC output signals. SINAD (dB) = 20 log (SignalRMS/NoiseRMS)
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples.
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19
2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCs MAX1136-MAX1139
Effective Number of Bits
Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. With an input range equal to the ADC's full-scale range, calculate the ENOB as follows:
SignalRMS SINAD(dB) = 20 x log NoiseRMS + THDRMS
ANALOG INPUTS
Typical Operating Circuit
0.1mF 3.3V or 5V
VDD AIN0 AIN1
MAX1136 MAX1137 MAX1138 AIN3**/REF MAX1139
0.1mF GND
*RS SDA SCL *RS
ENOB = (SINAD - 1.76)/6.02
CREF
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS sum of the input signal's first five harmonics to the fundamental itself. This is expressed as:
THD = 20 x log V 2 +V 2 +V 2 +V 2 3 4 5 2 V1
5V
5V
RP
RP
mC
SDA SCL
*OPTIONAL **AIN11/REF (MAX1138/MAX1139)
where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd through 5th order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest distortion component.
TOP VIEW
Pin Configurations
Chip Information
MAX1136/MAX1137 TRANSISTORS COUNT: 11,362 MAX1138/MAX1139 TRANSISTORS COUNT: 12,956 PROCESS: BiCMOS
AIN0 AIN1 AIN2
1 2 3
8 7
VDD GND SDA SCL
MAX1136 MAX1137
6 5
AIN3/REF 4
MAX
AIN0 1 AIN1 2
16 AIN8 15 AIN9 14 AIN10
Selector Guide
PART MAX1136EUA MAX1137EUA MAX1138EEE MAX1139EEE INPUT CHANNELS 4 4 12 12 INTERNAL SUPPLY REFERENCE VOLTAGE (V) (V) 4.096 2.048 4.096 2.048 4.5 to 5.5 2.7 to 3.6 4.5 to 5.5 2.7 to 3.6
AIN2 3 AIN3 4 AIN4 5 AIN5 6 AIN6 7 AIN7 8
MAX1138 MAX1139
13 AIN11/REF 12 VDD 11 GND 10 SDA 9 SCL
QSOP
20
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2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
8LUMAXD.EPS
MAX1136-MAX1139
8
4X S
8
INCHES DIM A A1 A2 b c D e E H MIN 0.002 0.030 MAX 0.043 0.006 0.037
MILLIMETERS MAX MIN 0.05 0.75 1.10 0.15 0.95
y 0.500.1 0.60.1
E
H
1
0.60.1
1
D
L
S
BOTTOM VIEW
0.014 0.010 0.007 0.005 0.120 0.116 0.0256 BSC 0.120 0.116 0.198 0.188 0.026 0.016 6 0 0.0207 BSC
0.25 0.36 0.13 0.18 2.95 3.05 0.65 BSC 2.95 3.05 4.78 5.03 0.41 0.66 0 6 0.5250 BSC
TOP VIEW
A2
A1
A
e
c b L
SIDE VIEW
FRONT VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 8L uMAX/uSOP
APPROVAL DOCUMENT CONTROL NO. REV.
21-0036
J
1 1
______________________________________________________________________________________
21
2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel, 2-Wire Serial 10-Bit ADCs MAX1136-MAX1139
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QSOP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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